CVE-2025-40122

{
  "id": "CVE-2025-40122",
  "sourceIdentifier": "416baaa9-dc9f-4396-8d5f-8c081fb06d67",
  "published": "2025-11-12T11:15:41.677",
  "lastModified": "2026-10-19T21:10:00.160",
  "vulnStatus": "Deferred",
  "cveTags": [],
  "descriptions": [
    {
      "lang": "en",
      "value": "In the Linux kernel, the following vulnerability has been resolved:\n\nperf/x86/intel: Fix IA32_PMC_x_CFG_B MSRs access error\n\nWhen running perf_fuzzer on PTL, sometimes the below \"unchecked MSR\n access error\" is seen when accessing IA32_PMC_x_CFG_B MSRs.\n\n[   55.611268] unchecked MSR access error: WRMSR to 0x1986 (tried to write 0x0000000200000001) at rIP: 0xffffffffac564b28 (native_write_msr+0x8/0x30)\n[   55.611280] Call Trace:\n[   55.611282]  <TASK>\n[   55.611284]  ? intel_pmu_config_acr+0x87/0x160\n[   55.611289]  intel_pmu_enable_acr+0x6d/0x80\n[   55.611291]  intel_pmu_enable_event+0xce/0x460\n[   55.611293]  x86_pmu_start+0x78/0xb0\n[   55.611297]  x86_pmu_enable+0x218/0x3a0\n[   55.611300]  ? x86_pmu_enable+0x121/0x3a0\n[   55.611302]  perf_pmu_enable+0x40/0x50\n[   55.611307]  ctx_resched+0x19d/0x220\n[   55.611309]  __perf_install_in_context+0x284/0x2f0\n[   55.611311]  ? __pfx_remote_function+0x10/0x10\n[   55.611314]  remote_function+0x52/0x70\n[   55.611317]  ? __pfx_remote_function+0x10/0x10\n[   55.611319]  generic_exec_single+0x84/0x150\n[   55.611323]  smp_call_function_single+0xc5/0x1a0\n[   55.611326]  ? __pfx_remote_function+0x10/0x10\n[   55.611329]  perf_install_in_context+0xd1/0x1e0\n[   55.611331]  ? __pfx___perf_install_in_context+0x10/0x10\n[   55.611333]  __do_sys_perf_event_open+0xa76/0x1040\n[   55.611336]  __x64_sys_perf_event_open+0x26/0x30\n[   55.611337]  x64_sys_call+0x1d8e/0x20c0\n[   55.611339]  do_syscall_64+0x4f/0x120\n[   55.611343]  entry_SYSCALL_64_after_hwframe+0x76/0x7e\n\nOn PTL, GP counter 0 and 1 doesn't support auto counter reload feature,\nthus it would trigger a #GP when trying to write 1 on bit 0 of CFG_B MSR\nwhich requires to enable auto counter reload on GP counter 0.\n\nThe root cause of causing this issue is the check for auto counter\nreload (ACR) counter mask from user space is incorrect in\nintel_pmu_acr_late_setup() helper. It leads to an invalid ACR counter\nmask from user space could be set into hw.config1 and then written into\nCFG_B MSRs and trigger the MSR access warning.\n\ne.g., User may create a perf event with ACR counter mask (config2=0xcb),\nand there is only 1 event created, so \"cpuc->n_events\" is 1.\n\nThe correct check condition should be \"i + idx >= cpuc->n_events\"\ninstead of \"i + idx > cpuc->n_events\" (it looks a typo). Otherwise,\nthe counter mask would traverse twice and an invalid \"cpuc->assign[1]\"\nbit (bit 0) is set into hw.config1 and cause MSR accessing error.\n\nBesides, also check if the ACR counter mask corresponding events are\nACR events. If not, filter out these counter mask. If a event is not a\nACR event, it could be scheduled to an HW counter which doesn't support\nACR. It's invalid to add their counter index in ACR counter mask.\n\nFurthermore, remove the WARN_ON_ONCE() since it's easily triggered as\nuser could set any invalid ACR counter mask and the warning message\ncould mislead users."
    },
    {
      "lang": "es",
      "value": "En el kernel de Linux, la siguiente vulnerabilidad ha sido resuelta:\n\nperf/x86/intel: Corrección del error de acceso a los MSR IA32_PMC_x_CFG_B\n\nAl ejecutar perf_fuzzer en PTL, a veces se observa el siguiente “error de acceso MSR no verificado” al acceder a los MSR IA32_PMC_x_CFG_B.\n\n[ 55.611268] error de acceso MSR no verificado: WRMSR a 0x1986 (intentó escribir 0x0000000200000001) en rIP: 0xffffffffac564b28 (native_write_msr+0x8/0x30)\n[ 55.611280] Traza de Llamada:\n[ 55.611282] <TASK>\n[ 55.611284] ? intel_pmu_config_acr+0x87/0x160\n[ 55.611289] intel_pmu_enable_acr+0x6d/0x80\n[ 55.611291] intel_pmu_enable_event+0xce/0x460\n[ 55.611293] x86_pmu_start+0x78/0xb0\n[ 55.611297] x86_pmu_enable+0x218/0x3a0\n[ 55.611300] ? x86_pmu_enable+0x121/0x3a0\n[ 55.611302] perf_pmu_enable+0x40/0x50\n[ 55.611307] ctx_resched+0x19d/0x220\n[ 55.611309] __perf_install_in_context+0x284/0x2f0\n[ 55.611311] ? __pfx_remote_function+0x10/0x10\n[ 55.611314] remote_function+0x52/0x70\n[ 55.611317] ? __pfx_remote_function+0x10/0x10\n[ 55.611319] generic_exec_single+0x84/0x150\n[ 55.611323] smp_call_function_single+0xc5/0x1a0\n[ 55.611326] ? __pfx_remote_function+0x10/0x10\n[ 55.611329] perf_install_in_context+0xd1/0x1e0\n[ 55.611331] ? __pfx___perf_install_in_context+0x10/0x10\n[ 55.611333] __do_sys_perf_event_open+0xa76/0x1040\n[ 55.611336] __x64_sys_perf_event_open+0x26/0x30\n[ 55.611337] x64_sys_call+0x1d8e/0x20c0\n[ 55.611339] do_syscall_64+0x4f/0x120\n[ 55.611343] entry_SYSCALL_64_after_hwframe+0x76/0x7e\n\nEn PTL, los contadores GP 0 y 1 no soportan la característica de recarga automática de contador, por lo tanto, activaría un #GP al intentar escribir 1 en el bit 0 del MSR CFG_B, lo que requiere habilitar la recarga automática de contador en el contador GP 0.\n\nLa causa raíz de este problema es que la verificación de la máscara de contador de recarga automática (ACR) desde el espacio de usuario es incorrecta en la función auxiliar intel_pmu_acr_late_setup(). Esto lleva a que una máscara de contador ACR inválida desde el espacio de usuario podría establecerse en hw.config1 y luego escribirse en los MSR CFG_B y activar la advertencia de acceso MSR.\n\nPor ejemplo, el usuario puede crear un evento perf con una máscara de contador ACR (config2=0xcb), y solo se crea 1 evento, por lo que “cpuc->n_events” es 1.\n\nLa condición de verificación correcta debería ser “i + idx >= cpuc->n_events” en lugar de “i + idx > cpuc->n_events” (parece un error tipográfico). De lo contrario, la máscara de contador se recorrería dos veces y un bit “cpuc->assign[1]” inválido (bit 0) se establecería en hw.config1 y causaría un error de acceso MSR.\n\nAdemás, también se debe verificar si los eventos correspondientes a la máscara de contador ACR son eventos ACR. Si no, filtrar esta máscara de contador. Si un evento no es un evento ACR, podría programarse en un contador de hardware que no soporta ACR. Es inválido añadir su índice de contador en la máscara de contador ACR.\n\nAdemás, eliminar el WARN_ON_ONCE() ya que se activa fácilmente, puesto que el usuario podría establecer cualquier máscara de contador ACR inválida y el mensaje de advertencia podría inducir a error a los usuarios."
    }
  ],
  "affected": [
    {
      "source": "416baaa9-dc9f-4396-8d5f-8c081fb06d67",
      "affectedData": [
        {
          "vendor": "Linux",
          "product": "Linux",
          "defaultStatus": "unaffected",
          "programFiles": [
            "arch/x86/events/intel/core.c"
          ],
          "repo": "https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git",
          "versions": [
            {
              "version": "ec980e4facef8110f6fce27e5b6344660117f01f",
              "lessThan": "c6cca4213b618c92e4972919ee568f0fb87313b1",
              "versionType": "git",
              "status": "affected"
            },
            {
              "version": "ec980e4facef8110f6fce27e5b6344660117f01f",
              "lessThan": "43796f30507802d93ead2dc44fc9637f34671a89",
              "versionType": "git",
              "status": "affected"
            }
          ]
        },
        {
          "vendor": "Linux",
          "product": "Linux",
          "defaultStatus": "affected",
          "programFiles": [
            "arch/x86/events/intel/core.c"
          ],
          "repo": "https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git",
          "versions": [
            {
              "version": "6.16",
              "status": "affected"
            },
            {
              "version": "0",
              "lessThan": "6.16",
              "versionType": "semver",
              "status": "unaffected"
            },
            {
              "version": "6.17.3",
              "lessThanOrEqual": "6.17.*",
              "versionType": "semver",
              "status": "unaffected"
            },
            {
              "version": "6.18",
              "lessThanOrEqual": "*",
              "versionType": "original_commit_for_fix",
              "status": "unaffected"
            }
          ]
        }
      ]
    }
  ],
  "metrics": {},
  "references": [
    {
      "url": "https://git.kernel.org/stable/c/43796f30507802d93ead2dc44fc9637f34671a89",
      "source": "416baaa9-dc9f-4396-8d5f-8c081fb06d67"
    },
    {
      "url": "https://git.kernel.org/stable/c/c6cca4213b618c92e4972919ee568f0fb87313b1",
      "source": "416baaa9-dc9f-4396-8d5f-8c081fb06d67"
    }
  ]
}